The present invention relates generally to design and manufacturing methods of circuits that use multiple integrated circuits. Specifically, this disclosure relates to methods and systems for fabrication of interconnect structures with varied dimensions for production of multi-die devices.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it may be understood that these statements are to be read in this light, and not as admissions of prior art.
Many electrical devices may divide the tasks and functionalities across different circuitries, such as programmable logic devices, processors, memory, and other integrated circuits. The multiple integrated circuits may be assembled in a circuit board or mounted to a substrate to form an integrated monolithic die. Monolithic dies may provide improved performance when compared to other systems such as a circuit board, as the customized interconnect structure may provide reduced latency, improved bandwidth, reduced power consumption, elimination or mitigation of dedicated communication circuitry, (e.g., transceivers, serializers, deserializers) and/or less expensive manufacturing. For example, many mobile devices employ a System-on-a-Chip, a monolithic die that may have a microprocessor, a graphics unit, and a network controller, among other integrated circuits.
Monolithic dies having multiple integrated circuits may include an interconnect composed of electrical routes formed in the substrate of the monolithic die. The interconnect may enable communication between the integrated circuits mounted to the substrate and between the integrated circuits and other circuitries coupled to the monolithic die by providing electrical coupling between the various circuitries. In particular, the coupling between the integrated circuits and the interconnect may take place through contacts between integrated circuit terminals and a top metal layer of the interconnect that is exposed in the surface of the substrate.
As different types of integrated circuits may be mounted to different regions of the substrate, each region of the substrate may have different specifications for the top metal layer contacts. Specifications for the contact may include geometrical considerations, such as route density, metal thickness, or contact area. These specifications may be due to differences in power requirements, surface area availability, and delays due to parasitic impedance effects (e.g., resistance-capacitance delays) among other characteristics. For example, a microprocessor IC may be coupled to a region of the top metal layer with higher density of contacts, whereas a programmable logic device may be coupled to a region of the top metal layer with lower density of contacts. The fabrication of top metal layers having multiple regions with different geometrical specifications can be very challenging and, as a result, certain monolithic dies may instead employ compromise solutions using a single geometric specification that prevent maximum performance for the monolithic die. As the clocking speed increase and circuit scale decreases, the performance degradation observed in compromise solutions becomes critical.